As integrated circuits have become increasingly smaller, electrically conductive structures within the integrated circuits are placed increasingly closer together. This situation tends to enhance the inherent problem of parasitic capacitance between adjacent electrically conductive structures. Thus, new electrically insulating materials have been devised for use between electrically conductive structures, to reduce such capacitance problems. The new electrically insulating materials typically have lower dielectric constants, and thus are generally referred to as low k materials. While low k materials help to resolve the capacitance problems described above, they unfortunately tend to introduce new challenges.
Low k materials are typically filled with small voids that help reduce the material's effective dielectric constant. Thus, there is less of the material itself within a given volume, which tends to reduce the structural strength of the material. The resulting porous and brittle nature of such low k materials presents new challenges in both the fabrication and packaging processes. Unless special precautions are taken, the robustness and reliability of an integrated circuit that is fabricated with low k materials may be reduced from that of an integrated circuit that is fabricated with traditional materials, because low k materials differ from traditional materials in properties such as thermal coefficient of expansion, moisture absorption, adhesion to adjacent layers, mechanical strength, and thermal conductivity.
Low k materials are typically more brittle and have a lower breaking point than other materials. One reason for this is the porosity of the low k material, where a significant percentage of its physical volume is filled with voids. Thus, integrated circuits containing low k materials are inherently more prone to breaking or cracking during processes where physical contact is made with the integrated circuit surface, such as wire bonding and electrical probing, or processes that cause bending stresses such as mold curing, underfill curing, solder ball reflow, chemical mechanical polishing, or temperature cycling.
As integrated circuits have become smaller, they have shrunk not only in the amount of surface area required by the circuit, but also in the thicknesses of the various layers by which they are formed. As the thicknesses of the layers has decreased, it has become increasingly important to planarize a given layer prior to forming a subsequent overlying layer. One of the methods used for such planarization is called chemical mechanical polishing. During chemical mechanical polishing, the surface of the layer to be planarized, thinned, or both is brought into contact with the surface of a polishing pad. The pad and the substrate are rotated and translated relative to each other in the presence of a polishing fluid, which typically contains both physical erosion particles and chemical erosion compounds.
Unfortunately, the need to planarize the layers of an integrated circuit using traditional chemical mechanical polishing has become a problem, because the amount of down force and friction required to adequately erode a layer using chemical mechanical polishing has become great enough to crush, shear, or otherwise damage the increasingly delicate underlying low k layers as they are reduced in thickness with the general reduction in the size of integrated circuits.
For example, in copper dual damascene processing, there is a step to remove unwanted portions of a deposited copper layer from an upper surface of an integrated circuit. New integrated circuit designs place delicate low k layers somewhere beneath the copper layer to be removed. Traditional chemical mechanical polishing processes tend to be too rough during the removal of the copper layer, and damage the low k layer. Electropolishing is a more gentle method than chemical mechanical polishing, and has also been used to remove electrically conductive layers, such as copper. However, electropolishing tends to be unable to break through the oxidation on the surface of the copper layer, and thus is also inadequate for removing the copper layer. In addition, electropolishing also tends to not be able to remove the barrier layer and seed layer that often underlie the copper layer.
There is a need, therefore, for a new system for use in integrated circuit fabrication, which helps to alleviate one or more of the challenges mentioned above, and enables layers within an integrated circuit to be planarized or otherwise removed without damaging delicate underlying layers.